1. Field of the Invention
The invention relates to a method of forming a semiconductor device and, more particularly, to a method of forming a fin field effect transistor using a damascene process.
2. Description of Related Art
With the recent trend toward smaller semiconductor devices, field effect transistors of semiconductor devices (hereinafter referred to as “transistors”) have been scaled down. However, the short channel effect or drain induced barrier lower (DIBL) phenomenon makes it difficult to scale down transistors further. In view of the foregoing, fin transistors have been proposed. A typical fin transistor includes a fin vertically protruding from a substrate and a gate electrode crossing the fin. The gate electrode of the fin transistor is disposed on both sidewalls of a thin fin, thereby enhancing the controllability of a channel of the gate electrode and also suppressing the short channel effect or DIBL phenomenon.
A conventional method of forming a fin field effect transistor is described with reference to FIG. 1 through FIG. 3.
Referring to FIG. 1, a substrate 1 is selectively etched to form a vertically extending fin 2. A silicon oxide layer is formed on the entire surface of the substrate 1 to fill the etched region of the substrate 1. The silicon oxide layer is planarized to form a filling oxide pattern 3 along the sidewalls of the fin 2, until the fin 2 is exposed.
A nitride layer 4 is formed on the entire surface of the substrate 1. The nitride layer 4 is patterned to form a preliminary groove 5 crossing the fin 2. The preliminary groove 5 partially exposes the top surface of the fin 2 and the filling oxide pattern 3 disposed on opposite sides adjacent to the top surface of the exposed fin 2.
Referring to FIG. 2 and FIG. 3, the filling oxide pattern 3 exposed by the preliminary groove 5 is anisotropically etched to expose both sidewalls of the fin 2, using the nitride layer 4 as a mask. The etched region 6 of the filling oxide pattern 3 and the preliminary groove 5 constitute a groove 7.
A gate oxide layer 8 is formed on the substrate 1 having the groove 7. A gate electrode 9 is formed on the gate oxide layer 8 to fill the groove 7. The nitride layer 4 is removed to expose the top surface of the fin 2 disposed at both sides of the gate electrode 9.
Using the gate electrode 9 as a mask, impurities are implanted to form a source/drain region 10 at opposite sides adjacent to the gate electrode 9.
In the above-described conventional method, following formation of the fin 2, a trimming process may be performed to minutely control the width of the fin 2. According to the trimming process, a thermal oxide layer is formed on the surface, including the sidewalls, of the fin 2. The thermal oxide layer is removed using a wet etch, thereby smoothening the sidewalls of the fin 2 and also controlling the width of the fin 2. Preferably, only the width of a channel area disposed below the gate electrode 9 is controlled. If the width of the source/drain region 10 is also reduced, a contact area between a later-formed interconnection (not shown) and the source/drain region 10 is reduced and the contact resistance is increased. Therefore, the trimming process may be performed following formation of the groove 7 and prior to formation of the gate oxide layer 8. Even in this case, various problems may occur.
Specifically, a thermal oxide layer formed in the trimming process and the filling oxide pattern 3 are made of silicon oxide, and the wet etch of the trimming process is an isotropic etch. The thermal oxide layer of the fin 2, as well as the lower inner sidewalls of the groove 7, is etched in the wet etch of the trimming process. Since this leads to an increase in the width of the lower portion of groove 7, the line width of the gate electrode 9 formed on both sidewalls of the fin 2 may increase. As a result, the gate electrode 9 and the source/drain region 10 formed on the both sidewalls of the fin 2 may be shorted by an interconnection (not shown) connected to the source/drain region 10. Further, an overlap area of the gate electrode 9 and the source/drain region 10 is widened to increase a parasitic capacitance created by the gate electrode 9 and the source/drain region 10. Thus, the operating speed of the fin transistor may be lowered (i.e., the fin transistor may be degraded).
Moreover, the conventional method may cause other problems. Because impurities for forming the source/drain region 10 are implanted through the top surface of the fin 2 disposed on opposite sides adjacent to the gate electrode 9, the impurity concentration of the source/drain region may vary with portions of the source/drain region 10. Particularly, the impurity concentration in portions of the source/drain region 10 formed on both sidewalls of the fin 2 may be lower than that in portions of the source/drain regions 10 formed on the top surface of the fin 2. Thus, turn-on current flowing through a channel region formed on both sidewalls of the fin 2 may be decreased, thereby degrading electrical characteristics of the fin transistor.